Epitaxial deposition of GeSi layers for Ge contents from 0 to 30% has by now become common. This work extends the alloy range to 100% -- the deposition of pure epitaxial germanium on silicon and the integration of n-channel field effect transistors in the resulting material.

Germanium exhibits substantially higher low-field mobility than silicon for both electrons and holes, making it an attractive target for integration with silicon substrates. Other compelling features of the material are its much-reduced direct bandgap and its close lattice-match with GaAs. This work, however, focuses on the application of field effect transistors in Ge on Si.

Due to the 4% linear lattice mismatch between Ge and Si, the critical thickness for the deposition of strained (001) Ge on a (001) Si surface is only a few monolayers. Thus the lattice mismatch must be accommodated through the formation of defects. Graded buffer layers are one strategy for defect management. By carefully grading the alloy from pure silicon to pure germanium, the strain is relieved through the formation of buried misfit dislocations, leaving the surface layer with a sufficiently low defect density for the formation of high-quality semiconductor devices.

This talk will discuss the methodology and implementation of the epitaxial deposition of (001) germanium on (001) silicon using a graded buffer layer grown via chemical vapor deposition. It will then review issues associated with the integration of field-effect transistors in germanium, and show results of capacitors, diodes, and n-channel field effect transistors in the epitaxial material. Electrical results will then be analyzed and discussed.

Daniel Connelly
Stanford University, Department of Electrical Engineering
Center for Integrated Systems
Stanford, University
Stanford, CA 94305
phone: (650)725-3693
FAX: (650)725-6278
email: djconnel@nucleus.stanford.edu
web: http://nucleus.stanford.edu/~djconnel/research/